The present invention pertains to microprocessing devices and more particularly to a programmable wait state scheme for I/O with external devices.
Generally, whenever data is exchanged between two devices in a system, such as a microprocessing unit and a memory device, the system must ensure that the interaction between the two devices is synchronized. For example, present day microprocessors and microcontrollers are fabricated using technology which permits very high speed operation. Clock speeds of 300 MHz and higher are becoming commonplace. However peripheral devices, especially memory devices such as FLASH, SRAM, and EEPROM, typically are not capable of such high clock speeds.
A common approach to synchronizing with slower devices is to vary the duration of the bus cycle of the microprocessing device for each device access, sometimes referred to as xe2x80x9cbus stretching,xe2x80x9d by the use of wait states. The system""s address decoder decodes the address and determines which memory is to be selected. The system""s control logic then determines whether the memory is one that requires a wait state and asserts a WAIT signal line if required. The microprocessing core samples the signal line during a clock cycle and goes into a wait state (in essence a do-nothing state) for one clock cycle if the line is asserted. The micro samples the line at the next clock and resumes operation when the WAIT signal line is negated (de-asserted). This provides the slower memory device enough time to internally decode the address, access the memory, and allow the data at its output buffers to stabilize.
One prior art technique of using wait states includes storing a wait state number in the memory device itself. The computing device includes logic to access this number to determine the amount of time the bus cycle needs to be extended. This approach requires specialized devices which include logic to store a wait state number and to provide it to the computing device.
Another approach using wait states is used in interrupt-driven I/O devices. Logic in the program decoder detects the occurrence of certain I/O instructions and asserts a WAIT signal to suspend operation of the microprocessor for a period of time depending on the instruction. This approach is useful for access to slower I/O devices, where the microprocessor is paused during a return-from-interrupt instruction to give the slow I/O device time to perform its action.
A problem not addressed by the above is access to multiple memory devices, where a read access to a first device is not given enough time to complete before access to another device begins, resulting in a bus clash. The problem stems from the fact that the output driver of the first device is still driving the data bus that is common to both devices when access to the other device occurs. Unless enough time is allowed to pass before the second device performs an access, both devices will attempt to drive the bus. The result is garbled data and increased power consumption due to simultaneous access by both driver circuitry. However, this problem does not always present itself. For example, consecutive read operations from the same device do not pose problems with the drive circuitry. A write operation followed by a read operation, likewise, poses no problem with the drive circuitry.
What is needed is control circuitry in a microcomputing architecture that detects access to multiple memories and inserts wait states according to the type of I/O operation being performed. It is desirable to have circuitry that can detect which memory is being accessed and insert wait states accordingly. It is further desirable to have circuitry that inserts wait states depending on the sequence of I/O operations being performed.
In a computing device having first and second external memories, a method of accessing memory comprises associating a first wait state value to the first memory and a second wait state value to the second memory, then selecting the wait state values associated with a selected one of the memories, and reading the memory. Subsequent to the step of reading and prior to the next I/O operation, the CPU is put into a wait state for a period of time proportional to the selected wait state value; i.e. wait state x clock period.
However, if the next I/O operation is to the internal memory of the CPU, then the CPU does not enter a wait state prior to the I/O operation, but rather immediately proceeds with the I/O operation. If a read operation subsequent to the internal I/O operation is made to the originally selected external memory, then no wait state is entered and access immediately proceeds. If a read operation subsequent to the internal I/O operation is made to a different external memory, then the wait state is entered for a period of time proportional to the wait state associated with the originally selected external memory, timed from the completion of the read operation.
In accordance with the present invention, a microprocessing device includes a system bus to which external memories, core logic, and a memory controller are coupled. A wait state circuit generates a wait signal which puts the core logic in a wait state. Coupled to the wait state circuit is an external bus circuit which detects the sequence of memory accesses taking place on the system bus and activates the wait state circuit accordingly to put the core logic in a wait state. Coupled to the external bus circuit is data means for storing a data float wait state value for each memory device.
The data means outputs a data float wait state value to the external bus circuit in response to the memory device selected. The external bus circuit detects the occurrence of an external read followed by an access to another external memory and initiates a date float wait state for a period proportional to the wait state value corresponding to the accessed memory, i.e. wait state x clock period. However, if the external bus circuit detects a write operation followed by a read operation, then no data float wait state occurs, although a classical wait state may still occur. Similarly, if an external read operation is followed by an internal access, then no data float wait state will occur.